Generate separate stores for partially swizzled memory stores
Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
This commit is contained in:
Jeremy Hayes
parent
9158061398
commit
6d5b40f051
50 changed files with 31343 additions and 26594 deletions
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@ -1,71 +1,71 @@
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spv.310.bitcast.frag
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// Module Version 10000
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// Generated by (magic number): 8000a
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// Id's are bound by 153
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// Id's are bound by 179
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Capability Shader
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1: ExtInstImport "GLSL.std.450"
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MemoryModel Logical GLSL450
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EntryPoint Fragment 4 "main" 14 26 37 48 89 98 107 116 122 130 139 148
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EntryPoint Fragment 4 "main" 14 26 40 56 103 112 123 136 142 150 161 174
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ExecutionMode 4 OriginUpperLeft
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Source ESSL 310
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Name 4 "main"
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Name 9 "idata"
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Name 14 "f1"
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Name 26 "f2"
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Name 37 "f3"
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Name 48 "f4"
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Name 55 "udata"
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Name 85 "fdata"
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Name 89 "i1"
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Name 98 "i2"
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Name 107 "i3"
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Name 116 "i4"
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Name 122 "u1"
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Name 130 "u2"
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Name 139 "u3"
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Name 148 "u4"
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Name 40 "f3"
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Name 56 "f4"
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Name 63 "udata"
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Name 99 "fdata"
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Name 103 "i1"
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Name 112 "i2"
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Name 123 "i3"
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Name 136 "i4"
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Name 142 "u1"
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Name 150 "u2"
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Name 161 "u3"
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Name 174 "u4"
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Decorate 14(f1) RelaxedPrecision
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Decorate 148(u4) Flat
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Decorate 82 RelaxedPrecision
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Decorate 103(i1) RelaxedPrecision
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Decorate 103(i1) Flat
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Decorate 103(i1) Location 0
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Decorate 104 RelaxedPrecision
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Decorate 112(i2) RelaxedPrecision
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Decorate 112(i2) Flat
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Decorate 112(i2) Location 1
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Decorate 113 RelaxedPrecision
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Decorate 123(i3) RelaxedPrecision
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Decorate 124 RelaxedPrecision
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Decorate 136(i4) Flat
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Decorate 142(u1) RelaxedPrecision
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Decorate 143 RelaxedPrecision
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Decorate 150(u2) Flat
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Decorate 151 RelaxedPrecision
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Decorate 162 RelaxedPrecision
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2: TypeVoid
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3: TypeFunction 2
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6: TypeInt 32 1
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@ -83,44 +83,46 @@ spv.310.bitcast.frag
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25: TypePointer Input 24(fvec2)
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26(f2): 25(ptr) Variable Input
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28: TypeVector 6(int) 2
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35: TypeVector 12(float) 3
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36: TypePointer Input 35(fvec3)
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37(f3): 36(ptr) Variable Input
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39: TypeVector 6(int) 3
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46: TypeVector 12(float) 4
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47: TypePointer Input 46(fvec4)
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48(f4): 47(ptr) Variable Input
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53: TypeVector 17(int) 4
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54: TypePointer Function 53(ivec4)
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56: 53(ivec4) ConstantComposite 18 18 18 18
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59: TypePointer Function 17(int)
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65: TypeVector 17(int) 2
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73: TypeVector 17(int) 3
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84: TypePointer Function 46(fvec4)
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86: 12(float) Constant 0
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87: 46(fvec4) ConstantComposite 86 86 86 86
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88: TypePointer Input 6(int)
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89(i1): 88(ptr) Variable Input
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92: TypePointer Function 12(float)
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97: TypePointer Input 28(ivec2)
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98(i2): 97(ptr) Variable Input
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106: TypePointer Input 39(ivec3)
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107(i3): 106(ptr) Variable Input
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115: TypePointer Input 7(ivec4)
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116(i4): 115(ptr) Variable Input
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121: TypePointer Input 17(int)
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122(u1): 121(ptr) Variable Input
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129: TypePointer Input 65(ivec2)
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130(u2): 129(ptr) Variable Input
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138: TypePointer Input 73(ivec3)
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139(u3): 138(ptr) Variable Input
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147: TypePointer Input 53(ivec4)
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148(u4): 147(ptr) Variable Input
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35: 17(int) Constant 1
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38: TypeVector 12(float) 3
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39: TypePointer Input 38(fvec3)
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40(f3): 39(ptr) Variable Input
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42: TypeVector 6(int) 3
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51: 17(int) Constant 2
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54: TypeVector 12(float) 4
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55: TypePointer Input 54(fvec4)
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56(f4): 55(ptr) Variable Input
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61: TypeVector 17(int) 4
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62: TypePointer Function 61(ivec4)
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64: 61(ivec4) ConstantComposite 18 18 18 18
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67: TypePointer Function 17(int)
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73: TypeVector 17(int) 2
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83: TypeVector 17(int) 3
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98: TypePointer Function 54(fvec4)
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100: 12(float) Constant 0
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101: 54(fvec4) ConstantComposite 100 100 100 100
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102: TypePointer Input 6(int)
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103(i1): 102(ptr) Variable Input
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106: TypePointer Function 12(float)
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111: TypePointer Input 28(ivec2)
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112(i2): 111(ptr) Variable Input
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122: TypePointer Input 42(ivec3)
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123(i3): 122(ptr) Variable Input
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135: TypePointer Input 7(ivec4)
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136(i4): 135(ptr) Variable Input
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141: TypePointer Input 17(int)
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142(u1): 141(ptr) Variable Input
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149: TypePointer Input 73(ivec2)
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150(u2): 149(ptr) Variable Input
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160: TypePointer Input 83(ivec3)
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161(u3): 160(ptr) Variable Input
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173: TypePointer Input 61(ivec4)
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174(u4): 173(ptr) Variable Input
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4(main): 2 Function None 3
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5: Label
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9(idata): 8(ptr) Variable Function
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55(udata): 54(ptr) Variable Function
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85(fdata): 84(ptr) Variable Function
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63(udata): 62(ptr) Variable Function
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99(fdata): 98(ptr) Variable Function
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Store 9(idata) 11
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15: 12(float) Load 14(f1)
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16: 6(int) Bitcast 15
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@ -134,107 +136,143 @@ spv.310.bitcast.frag
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30: 7(ivec4) Load 9(idata)
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31: 28(ivec2) VectorShuffle 30 30 0 1
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32: 28(ivec2) IAdd 31 29
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33: 7(ivec4) Load 9(idata)
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34: 7(ivec4) VectorShuffle 33 32 4 5 2 3
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Store 9(idata) 34
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38: 35(fvec3) Load 37(f3)
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40: 39(ivec3) Bitcast 38
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41: 7(ivec4) Load 9(idata)
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42: 39(ivec3) VectorShuffle 41 41 0 1 2
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43: 39(ivec3) IAdd 42 40
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33: 19(ptr) AccessChain 9(idata) 18
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34: 6(int) CompositeExtract 32 0
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Store 33 34
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36: 19(ptr) AccessChain 9(idata) 35
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37: 6(int) CompositeExtract 32 1
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Store 36 37
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41: 38(fvec3) Load 40(f3)
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43: 42(ivec3) Bitcast 41
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44: 7(ivec4) Load 9(idata)
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45: 7(ivec4) VectorShuffle 44 43 4 5 6 3
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Store 9(idata) 45
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49: 46(fvec4) Load 48(f4)
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50: 7(ivec4) Bitcast 49
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51: 7(ivec4) Load 9(idata)
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52: 7(ivec4) IAdd 51 50
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Store 9(idata) 52
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Store 55(udata) 56
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57: 12(float) Load 14(f1)
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58: 17(int) Bitcast 57
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60: 59(ptr) AccessChain 55(udata) 18
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61: 17(int) Load 60
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62: 17(int) IAdd 61 58
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63: 59(ptr) AccessChain 55(udata) 18
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Store 63 62
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64: 24(fvec2) Load 26(f2)
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66: 65(ivec2) Bitcast 64
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67: 53(ivec4) Load 55(udata)
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68: 65(ivec2) VectorShuffle 67 67 0 1
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69: 65(ivec2) IAdd 68 66
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70: 53(ivec4) Load 55(udata)
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71: 53(ivec4) VectorShuffle 70 69 4 5 2 3
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Store 55(udata) 71
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72: 35(fvec3) Load 37(f3)
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74: 73(ivec3) Bitcast 72
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75: 53(ivec4) Load 55(udata)
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76: 73(ivec3) VectorShuffle 75 75 0 1 2
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77: 73(ivec3) IAdd 76 74
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78: 53(ivec4) Load 55(udata)
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79: 53(ivec4) VectorShuffle 78 77 4 5 6 3
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Store 55(udata) 79
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80: 46(fvec4) Load 48(f4)
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81: 53(ivec4) Bitcast 80
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82: 53(ivec4) Load 55(udata)
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83: 53(ivec4) IAdd 82 81
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Store 55(udata) 83
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Store 85(fdata) 87
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90: 6(int) Load 89(i1)
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91: 12(float) Bitcast 90
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93: 92(ptr) AccessChain 85(fdata) 18
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94: 12(float) Load 93
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95: 12(float) FAdd 94 91
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96: 92(ptr) AccessChain 85(fdata) 18
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Store 96 95
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99: 28(ivec2) Load 98(i2)
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100: 24(fvec2) Bitcast 99
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101: 46(fvec4) Load 85(fdata)
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102: 24(fvec2) VectorShuffle 101 101 0 1
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103: 24(fvec2) FAdd 102 100
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104: 46(fvec4) Load 85(fdata)
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105: 46(fvec4) VectorShuffle 104 103 4 5 2 3
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Store 85(fdata) 105
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108: 39(ivec3) Load 107(i3)
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109: 35(fvec3) Bitcast 108
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110: 46(fvec4) Load 85(fdata)
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111: 35(fvec3) VectorShuffle 110 110 0 1 2
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112: 35(fvec3) FAdd 111 109
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113: 46(fvec4) Load 85(fdata)
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114: 46(fvec4) VectorShuffle 113 112 4 5 6 3
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Store 85(fdata) 114
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117: 7(ivec4) Load 116(i4)
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118: 46(fvec4) Bitcast 117
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119: 46(fvec4) Load 85(fdata)
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120: 46(fvec4) FAdd 119 118
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Store 85(fdata) 120
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123: 17(int) Load 122(u1)
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124: 12(float) Bitcast 123
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125: 92(ptr) AccessChain 85(fdata) 18
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126: 12(float) Load 125
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127: 12(float) FAdd 126 124
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128: 92(ptr) AccessChain 85(fdata) 18
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Store 128 127
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131: 65(ivec2) Load 130(u2)
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132: 24(fvec2) Bitcast 131
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133: 46(fvec4) Load 85(fdata)
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134: 24(fvec2) VectorShuffle 133 133 0 1
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135: 24(fvec2) FAdd 134 132
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136: 46(fvec4) Load 85(fdata)
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137: 46(fvec4) VectorShuffle 136 135 4 5 2 3
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Store 85(fdata) 137
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140: 73(ivec3) Load 139(u3)
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141: 35(fvec3) Bitcast 140
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142: 46(fvec4) Load 85(fdata)
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143: 35(fvec3) VectorShuffle 142 142 0 1 2
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144: 35(fvec3) FAdd 143 141
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145: 46(fvec4) Load 85(fdata)
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146: 46(fvec4) VectorShuffle 145 144 4 5 6 3
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Store 85(fdata) 146
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149: 53(ivec4) Load 148(u4)
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150: 46(fvec4) Bitcast 149
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151: 46(fvec4) Load 85(fdata)
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152: 46(fvec4) FAdd 151 150
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Store 85(fdata) 152
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45: 42(ivec3) VectorShuffle 44 44 0 1 2
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46: 42(ivec3) IAdd 45 43
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47: 19(ptr) AccessChain 9(idata) 18
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48: 6(int) CompositeExtract 46 0
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Store 47 48
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49: 19(ptr) AccessChain 9(idata) 35
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50: 6(int) CompositeExtract 46 1
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Store 49 50
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52: 19(ptr) AccessChain 9(idata) 51
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53: 6(int) CompositeExtract 46 2
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Store 52 53
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57: 54(fvec4) Load 56(f4)
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58: 7(ivec4) Bitcast 57
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59: 7(ivec4) Load 9(idata)
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60: 7(ivec4) IAdd 59 58
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Store 9(idata) 60
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Store 63(udata) 64
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65: 12(float) Load 14(f1)
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66: 17(int) Bitcast 65
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68: 67(ptr) AccessChain 63(udata) 18
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69: 17(int) Load 68
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70: 17(int) IAdd 69 66
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71: 67(ptr) AccessChain 63(udata) 18
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Store 71 70
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72: 24(fvec2) Load 26(f2)
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74: 73(ivec2) Bitcast 72
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75: 61(ivec4) Load 63(udata)
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76: 73(ivec2) VectorShuffle 75 75 0 1
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77: 73(ivec2) IAdd 76 74
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78: 67(ptr) AccessChain 63(udata) 18
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79: 17(int) CompositeExtract 77 0
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Store 78 79
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80: 67(ptr) AccessChain 63(udata) 35
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81: 17(int) CompositeExtract 77 1
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Store 80 81
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82: 38(fvec3) Load 40(f3)
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84: 83(ivec3) Bitcast 82
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85: 61(ivec4) Load 63(udata)
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86: 83(ivec3) VectorShuffle 85 85 0 1 2
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87: 83(ivec3) IAdd 86 84
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88: 67(ptr) AccessChain 63(udata) 18
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89: 17(int) CompositeExtract 87 0
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Store 88 89
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90: 67(ptr) AccessChain 63(udata) 35
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91: 17(int) CompositeExtract 87 1
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Store 90 91
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92: 67(ptr) AccessChain 63(udata) 51
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93: 17(int) CompositeExtract 87 2
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Store 92 93
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94: 54(fvec4) Load 56(f4)
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95: 61(ivec4) Bitcast 94
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96: 61(ivec4) Load 63(udata)
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97: 61(ivec4) IAdd 96 95
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Store 63(udata) 97
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Store 99(fdata) 101
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104: 6(int) Load 103(i1)
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105: 12(float) Bitcast 104
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107: 106(ptr) AccessChain 99(fdata) 18
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108: 12(float) Load 107
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109: 12(float) FAdd 108 105
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110: 106(ptr) AccessChain 99(fdata) 18
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Store 110 109
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113: 28(ivec2) Load 112(i2)
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114: 24(fvec2) Bitcast 113
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115: 54(fvec4) Load 99(fdata)
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116: 24(fvec2) VectorShuffle 115 115 0 1
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117: 24(fvec2) FAdd 116 114
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118: 106(ptr) AccessChain 99(fdata) 18
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119: 12(float) CompositeExtract 117 0
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Store 118 119
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120: 106(ptr) AccessChain 99(fdata) 35
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121: 12(float) CompositeExtract 117 1
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Store 120 121
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124: 42(ivec3) Load 123(i3)
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125: 38(fvec3) Bitcast 124
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126: 54(fvec4) Load 99(fdata)
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127: 38(fvec3) VectorShuffle 126 126 0 1 2
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128: 38(fvec3) FAdd 127 125
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129: 106(ptr) AccessChain 99(fdata) 18
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130: 12(float) CompositeExtract 128 0
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Store 129 130
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131: 106(ptr) AccessChain 99(fdata) 35
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132: 12(float) CompositeExtract 128 1
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Store 131 132
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133: 106(ptr) AccessChain 99(fdata) 51
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134: 12(float) CompositeExtract 128 2
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Store 133 134
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137: 7(ivec4) Load 136(i4)
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138: 54(fvec4) Bitcast 137
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139: 54(fvec4) Load 99(fdata)
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140: 54(fvec4) FAdd 139 138
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Store 99(fdata) 140
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143: 17(int) Load 142(u1)
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144: 12(float) Bitcast 143
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145: 106(ptr) AccessChain 99(fdata) 18
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146: 12(float) Load 145
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147: 12(float) FAdd 146 144
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148: 106(ptr) AccessChain 99(fdata) 18
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Store 148 147
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151: 73(ivec2) Load 150(u2)
|
||||
152: 24(fvec2) Bitcast 151
|
||||
153: 54(fvec4) Load 99(fdata)
|
||||
154: 24(fvec2) VectorShuffle 153 153 0 1
|
||||
155: 24(fvec2) FAdd 154 152
|
||||
156: 106(ptr) AccessChain 99(fdata) 18
|
||||
157: 12(float) CompositeExtract 155 0
|
||||
Store 156 157
|
||||
158: 106(ptr) AccessChain 99(fdata) 35
|
||||
159: 12(float) CompositeExtract 155 1
|
||||
Store 158 159
|
||||
162: 83(ivec3) Load 161(u3)
|
||||
163: 38(fvec3) Bitcast 162
|
||||
164: 54(fvec4) Load 99(fdata)
|
||||
165: 38(fvec3) VectorShuffle 164 164 0 1 2
|
||||
166: 38(fvec3) FAdd 165 163
|
||||
167: 106(ptr) AccessChain 99(fdata) 18
|
||||
168: 12(float) CompositeExtract 166 0
|
||||
Store 167 168
|
||||
169: 106(ptr) AccessChain 99(fdata) 35
|
||||
170: 12(float) CompositeExtract 166 1
|
||||
Store 169 170
|
||||
171: 106(ptr) AccessChain 99(fdata) 51
|
||||
172: 12(float) CompositeExtract 166 2
|
||||
Store 171 172
|
||||
175: 61(ivec4) Load 174(u4)
|
||||
176: 54(fvec4) Bitcast 175
|
||||
177: 54(fvec4) Load 99(fdata)
|
||||
178: 54(fvec4) FAdd 177 176
|
||||
Store 99(fdata) 178
|
||||
Return
|
||||
FunctionEnd
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue